Semiconductor chips typically comprise the bulk of the components in an electronic system. These semiconductor chips are also often the hottest part of the electronic system, and failure of the system can often be traced back to thermal overload on the chips. As such, accurate estimation of a semiconductor chip design's thermal conductance is a critical parameter of semiconductor chip design.
FIG. 1 is a schematic diagram illustrating an exemplary semiconductor chip 100. As illustrated, the semiconductor chip 100 comprises one or more semiconductor devices 102a-102n (hereinafter collectively referred to as “semiconductor devices 102”), such as transistors, resistors, capacitors, diodes and the like deposited upon a substrate 104 and coupled via a plurality of wires or interconnects 106a-106n (hereinafter collectively referred to as “interconnects 106”). These semiconductor devices 102 and interconnects 106 share power, thereby distributing a thermal gradient over the chip 100 that may range from 100 to 180 degrees Celsius in various regions of the chip 100. Moreover, the thermal conductivity over the chip 100 varies with the different materials (e.g., metal, dielectric, etc.) contained therein.
Many methods currently exist for performing thermal analysis of semiconductor chips designs, e.g., to ensure that a chip constructed in accordance with a given design will not overheat and trigger a failure when deployed within an intended system. Such conventional methods, however, typically fail to provide a complete or an entirely accurate picture of the chip's operating thermal gradient. For example, typical thermal analysis models attempt to solve the temperature on the chip substrate, but do not solve the temperature in a full three dimensions, e.g., using industry standards design, package and heat sink data. Moreover, most typical methods do not account for the sharing of power among semiconductor devices and interconnects, which distributes the heat field within the chip, as discussed above.
In addition, most conventional methods for modeling heat conducting paths within semiconductor chip designs are quite complex, as extraction of conductance values involves computation of the different shapes and materials within the semiconductor chip design. The practicality of such methods is thus impacted not only by the accuracy of the thermal data provided thereto, but also by the computational inefficiency.
Therefore, there is a need in the art for a method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance.